A storage system includes a cache memory which enables speedy reading or writing data requested by a host computer for read or write to improve responsivity to the host computer. The cache memory stores user data to be written to a storage device and, in addition, control information to control operation of the storage system.
A cache memory is typically configured with a volatile DRAM. There are three ways to access the DRAM: (1) read, (2) write, and (3) read-modify-write (RMW); one of the three ways is selected to access data held in the DRAM.
In a read, the address from which data is to be read and the data length are specified, so that the data at the address in the specified range is transferred in burst mode in units of lines of the DRAM. In other words, a line read accesses data by a predetermined data length; accordingly, even if an access to a small amount of data is intended, the operation results in accessing data preceding and subsequent to the target data inclusively.
In a read-modify-write, a small amount of data can be accessed, but a single command results in a read and a write performed in a series of operation; accordingly, unnecessary operation may be performed in reading data held in the DRAM or writing data to the DRAM.
For this reason, desired is a speedy access to a small amount of data held in a cache memory in some way other than the read-modify-write.
For such a speedy access to a cache memory, some techniques have been proposed that hierarchically provide a cache of an SRAM. For example, JP 2006-127251 A discloses a technique that employs an SRAM, which is smaller than a DRAM in size, as a cache memory to improve performance in memory access.
JP H10-207769 A discloses a cache memory including an SRAM cache memory, which operates at high speed, and a DRAM cache memory having a large storage capacity.
JP 2004-355810 A discloses a semiconductor storage device in which data frequently used is stored in a main cache (SRAM), data which is less frequently used in the data stored in the main cache is stored in a sub cache (SRAM), and the cached data is returned to a main memory (DRAM) in an interval between refresh operations or transfer operations of the main memory.